The performance of high speed computers increasingly demands higher performance packaging and interconnection methods, from the printed circuit board (PCB) level on up. As semiconductor devices are developed to be operated with higher frequencies and shorter rise-times, the properties of the PCB substrates become more important.
In order to build working high density laminated PCBs, it is necessary to employ high performance polymers as the dielectric material. The high performance polymers are those which have very low dielectric constants, typically below 3 and even below 2, in order to permit higher line densities without causing shorting, electromagnetic inductance or crosstalk between conductors. They also require lamination temperatures higher than those required by higher dielectric polymers, such as epoxy, which requires a laminating temperature of about or below 200 degrees C. Among these high performance polymers are flourocarbon polymers, such as PTFE (polytetrafluorethylene), PFA (PTFE and perfluoroalkoxy vinyl ether copolymer), polyimides, fluorinated polyimides, fluorinated cyanate esters, polysiloxane imioles, and polyphenyl quinoxilines. In order to electrically interconnect levels of circuitry in the Z-direction, i.e. in the direction normal to the plane, metallized through holes and vias are conventionally formed therebetween.
The term via is used when the opening terminates internally in a laminate layer, such as at a ground plane; the term through hole is used when the penetration continues to the opposite surface. For present purposes the term through hole will be used to encompass both through holes and vias.
As the required wiring density of higher performance printed circuit boards increases, the number of signal layers in the structure increases. Consequently, the number of interconnections between signal layers also significantly increases. The number of interconnections between signal layers is too high to be accommodated by conventional plated through hole (PTH) techniques. The limitation is due to the difficulties in drilling smaller holes, i.e. smaller than 6 mil, and plating in high aspect ratio holes (ratio of length to diameter).
It is clear therefore that the complexity of multilayer structures required for both first and second level high density packages cannot be achieved by conventional PCB or MLC (multilevel ceramic) technologies due to the process limitations of the conventional methods. A new method of interconnection other than soldered, plated through holes or screened vias is required.
Development of a parallel process, i.e. simultaneous lamination and interconnection, enables the fabrication of the multilayer structures by combining subunits or building blocks built, tested and repaired separately. The possibility of testing and repair of the subunits will greatly enhance overall product yield. Parallel processing is also very attractive in terms of shortened process time, and consequent overall cost savings.
While the concept of parallel processing typically either by parallel plates or by vacuum lamination is very attractive, it demands a new method of achieving electrical interconnections, often having high current carrying capabilities. One way of achieving interconnection is to prepare an eyelet shaped conductive pad called a land. As used in the practice of the present invention, the land provides a place where electrical contact can be made to a corresponding land at the surface of a second dielectric layer to which the first is to be laminated. In order to electrically connect two pads, conventional soldering may be an acceptable means in some situations. For example, a solder can be applied to the pads by an appropriate method, such as screening or plating, and reflowed during lamination. When the pads are connected to metallized holes, it is also possible to fill the holes with a solder. However, in high density packaging, with advanced dielectric materials, the use of such a solder is inadequate for making the land-to-land electrical contact. To give an example of the dimensions involved, in one high density package, Cu line thickness is 8 microns. It is 250 microns between lands. There are either one or two lines between lands, and the linewidth is either 25 microns or 50 microns. The closeness of adjacent lands and their small dimensions present the potential for solder bridging, shorting between the pads caused by the melted solder squeezed out during lamination. The problem is exacerbated by the fact that the laminated layers can be built up successively to fifty or more layers, with repeated soldering followed by repeated lamination under heat and pressure. Each time the lamination would occur, solder would reflow, and the opportunity for bridging would be presented anew.
Transient liquid bonding (TLB) is a diffusion bonding technique which involves depositing on different conductive surfaces metals which together are capable of forming a eutectic melt. The surfaces to be bonded must be comprised of a highly conductive material such as copper, and are coated with the metals, brought into physical contact with one another and are heated above the eutectic temperature to form a melt. Solidification of this thin, liquid region bonds the metallic surfaces together. Recent work, such as described in Ser. No. 07/382,073, "Bonding of Metallic Surfaces" to Wilcox et al, filed Jul. 17, 1989, now U.S. Pat. No. 5,038,996, which is a continuation of Ser. No. 07/256,534, now abandoned, filed Oct. 12, 1988, commonly assigned to the present assignee, has applied the techniques of transient liquid bonding to connect the copper terminal pins of surface mounted semiconductor devices to copper lands on a second level electronic package such as a printed circuit board or card. Since the TLB process does not require the use of flux and uses minimal amounts of solder, bridging is reduced as compared to conventional soldering. A solder which, having formed a eutectic melt at a low temperature, would solidify to form an alloy which would not then melt until a temperature is reached that is higher than temperatures required in subsequent device processing, without forming brittle intermetallics in the process, would provide many advantages over known techniques. If the soldering could be performed simultaneously with the lamination of the multilayer high performance board, the joining would be a more efficient and reliable process than heretofore.